CISCO 千兆交换路由器(GSR)体系结构
Cisco 12012 全交换总线结构
CISCO GSR仍然是基于对传统路由器的改进，增强了路由器处理器（RP）和增加了专用的ASIC接口处理器。采用接口分布式处理和单一（或冗余）的CPU处理，仍然基于总线结构。
GSR 接口卡
GSR 路由处理器
采用RISC 处理器：
IDT R5000 RedUCed Instruction Set Computing (RISC) processor used for the CPU. The CPU runs at an external bus clock speed of 100 MHz and an internal clock speed of 200 MHz.
配置内存包括：
DRAMM—Up to 256 megabytes (MB) of parity-protected, extended data output (EDO) dynamic random-Access memory (DRAM) on two, 60-nanosecond (ns), dual in-line memory modules (DIMMs). 128 MB of DRAM is the minimum shipping configuration for the GRP.
SRAM—512 kilobytes (KB) of static random-access memory (SRAM) for secondary CPU cache memory functions. (SRAM is not user configurable or field upgradeable.)
NVRAM—512 KB of nonvolatile RAM (NVRAM). (NVRAM is not user configurable or field upgradeable.)
Memory—Most of the additional memory components used by the system, including onboard Flash memory and up to two Personal Computer Memory Card International Association (PCMCIA)-based Flash memory cards.
Juniper骨干路由器体系结构
体系结构
两个要害部件：Packet Forwarding Engine (PFE)、Routing Engine，, which are connected via a 100-Mbps link.
_ PFE完成分组的转发，包括Flexible PIC Concentrators (FPCs), physical interface cards (PICs), System Control Board (SCB), and state-of-the-art ASICs.
_ Routing Engine维护路由表，控制路由选择协议。Intel-based PCI platform running JUNOS software.
Leading-edge ASICs
ASICs deliver a comprehensive hardware-based system for packet processing, including route lookups, filtering, sampling, rate limiting, load balancing, buffer management, switching, encapsulation, and de-encapsulation functions. To ensure a non-blocking forwarding path, all channels between the ASICs are oversized, dedicated paths.
Internet Processor II ASIC
The Internet Processor II™ ASIC supports a lookup rate of over 40 Mpps. With over one million gates, the Internet Processor II ASIC delivers high-speed forwarding performance with advanced services, such as filtering and sampling, enabled. It is the largest, fastest, and most advanced ASIC ever implemented on a router platform and deployed in the Internet.
Distributed Buffer Manager ASICs
The Distributed Buffer Manager ASICs allocate incoming data packets throughout shared memory on the FPCs. This singlestage buffering improves performance by requiring only one write to and one read from shared memory. There are no extraneous steps of copying packets from input buffers to output buffers. The shared memory is completely nonblocking, which in turn, prevents head-of-line blocking.
I/O Manager ASICs
Each FPC is equipped with an I/O Manager ASIC that supports packet parsing, packet prioritizing, and queuing. This ASIC divides the packets, stores them in shared memory (managed by the Distributed Buffer Manager ASICs), and reassembles the packets for transmission.
Media-specific ASICs
The media-specific ASICs perform physical layer functions, such as framing. Each PIC is equipped with an ASIC or FPGA that performs control functions tailored to the PIC’s media type.
Packet Forwarding Engine
The PFE provides Layer 2 and Layer 3 packet switching, route lookups, and packet forwarding. The Internet Processor II ASIC forwards up to 40 Mpps for all packet sizes. The throughput is 40+ Gbps.
The PFE supports the same ASIC-based features supported by other M-series routers. For example, class-of-service features include rate limiting, classification, priority queuing, Random Early Detection, and Weighted Round Robin to increase bandwidth efficiency. Filtering and sampling are also available for restricting access, increasing security, and analyzing network traffic.
Finally, the PFE delivers maximum stability during exceptional conditions, while also providing a significantly lower part count. This stability reduces power consumption and increases mean time between failure.
Flexible PIC Concentrators
The FPCs house PICs and connect them to the rest of the PFE. There is a dedicated, full-duplex 3.2-Gbps channel between each FPC and the core of the PFE.
You can insert up to eight FPCs in an M40 chassis. The OC-48c/STM-16 PIC occupies an entire FPC. Otherwise, each FPC supports up to four PICs in any combination, providing unparalleled interface density and configuration flexibility. Each FPC contains shared memory for storing data packets received; the Distributed Buffer Manager ASICs on the SCB manage this memory. In addition, the FPC houses the I/O Manager ASIC, which performs a variety of queue management and class-of-service functions.
Physical Interface Cards
PICs provide a complete range of fiber optic and electrical transmission interfaces to the network. The M40 router offers flexibility and conserves rack space by supporting a wide variety of PICs and port densities. All PICs occupy one of four PIC spaces per FPC except for the OC-48c/STM-16 PIC, which occupies an entire FPC slot. An additional Tunnel Services PIC enables the M40 router to function as the ingress or egress point of an IP-IP unicast tunnel, a Cisco generic routing encapsulation (GRE) tunnel, or a Protocol Independent Multicast - Sparse Mode (PIM-SM) tunnel.
For a list of available PICs, see the M-series Internet Backbone Routers Physical Interface Cards datasheet.
System Control Board
Hosting the Internet Processor II ASIC, the SCB performs sampling, filtering, and packet forwarding decisions. The SCB also houses a processor that processes exception and control packets, monitors system components, and controls FPC resets.
Routing Engine
The Routing Engine maintains the routing tables and controls the routing protocols, as well as the JUNOS software processes that control the router’s interfaces, the chassis components, system management, and user access to the router. These routing and software processes run on top of a kernel that interacts with the PFE. _ The Routing Engine processes all routing protocol updates from the network, so PFE performance is not affected.
_ The Routing Engine constructs and maintains routing tables with a complete set of Internet features and provides full flexibility for advertising, filtering, and modifying routes. Routing policies are set according to route parameters, such as prefixes, prefix lengths, and BGP attributes.
JUNOS Internet Software
JUNOS software is optimized to scale to large numbers of network interfaces and routes. The software consists of a series of system processes running in protected memory on top of an independent operating system. The modular design improves reliability by protecting against system-wide failure and by preventing the failure of one process from affecting the other software processes. JUNOS software offers unmatched configuration flexibility by providing an XML-based JUNOScript™ API in addition to the CLI interface.
总结和观点
CISCO从1984年开发出他的第一台路由器到今天网络技术发展经历的是一个多元化到IP统一的发展过程,其实至今网络应用中也还存在大量的SNA、AppleTalk、TokenRing、FDDI等。CISCO长期占据市场绝对优势也在于他的产品可以提供完全的解决方案。到今天，这成了CISCO的优势，也在一定程度上成为了CISCO的包袱。
我们再看看Juniper推出第一台路由器的时候，IP统一的趋势已经浮出水面，骨干网络上IP与ATM的争论也几乎证实骨干网络上跑IP数据包将成为技术发展趋势。这时候Juniper推出第一台骨干路由器，他就看准了IP技术这一个潮流。他没有这个包袱，而且不准确的说可能至今Juniper还没有推出支持SNA、AppleTalk、TokenRing、FDDI的路由器。
从硬件结构上面可以看出，CISCO坚持的是RISC CPU的方式，也许CISCO认为他的网络设备基于强大的IOS软件其功能扩展能力非常强而一直认为自己的软件厂商。Juniper的路由器增加了许多专用的ASIC处理芯片，而且其本身的软件设计的时候没有CISCO那样那么多的包袱，所以在他特定功能内Juniper的性能显得比强出CISCO。也许我们应该承认 Juniper在ASIC等基于硬件方面的技术确实比CISCO先进，也有说法说是Juniper路由器最初设计者是从CISCO的ASIC部门离开的，虽然后面这种说法可能没有根据，但从Juniper产品体系结构可以看出Juniper似乎坚持的是他的硬件处理能力和ASIC设计方面的技术优势。我们没有理由说CISCO确GSR 12012只有60G背板处理能力就不如其背板处理能力可达256G的6509多层交换机。也许CISCO放弃多年来最终对自己的定位——软件厂商，他也许可以集中力量在6509上面发展L3处理能力和ASIC技术，这也就可能不会在某些方面不如Juniper，这也许就不会有现在在市场上取得非常成功的GSR了。
Juniper完全可以象国内路由器厂家，推出和CISCO的IOS完全相似的用户接口的网络操作系统，而且这样做确实有利于已经对CISCO配置界面熟悉的网络工程师使用Juniper网络设备。但Juniper没有这样做，Juniper推出的第一台路由器就是骨干网络路由器，Juniper自始至终就是把CISCO作为其竞争的打击的对手，而不是作为学习的对象。他的定位非常之高，后来也证实其定位对于市场运做帮助非常大。为什么华为的高端路由器一直没有取得巨大成功呢？在用户心中可能都觉得华为是在学习CISCO，其实国内的路由器厂商都有这样问题，不能说明他们高端路由器产品真的CISCO差很远，尤其性能价格比会比CISCO差很远。他们为了方便用户操作，采用的与CISCO相似的用户界面，而用户反过来常问的是这些厂家拥有自主知识产权的操作系统是不是从CISCO购买的？有几个厂家的产品考虑兼容性和成本的时候不是参考和研究过其他厂家的产品呢？
以上分析只是基于本人对核心路由器肤浅的熟悉，旨在抛砖引玉！
本人没有推广或配置过Juniper的路由器，也还没有在打标中遭遇推广Juniper路由器的竞争对手，因此非常希望业界前辈对于本人不成熟的观点给予指正！
